Monday, June 30, 2014

Principal Design Engineer

Intrinsix – Dallas

Principal Design Engineer (PDE) Candidate will provide hands-on technical design

leadership and be an individual contributor on ASIC/SoC and FPGA projects.

Candidate will be responsible for, and contribute to, all phases of an ASIC/SoC/FPGA

development starting from creation of an architectural specification through ASIC/SoC/

FPGA sign-off.


10+ years experience in high speed ASIC/SoC/FPGA developments.

Previous experience as ASIC/SoC/FPGA design lead.

Proficient in Verilog .

Experience with a wide variety of ASIC/FPGA vendor technologies.

Significant experience with Synopsys synthesis, static timing analysis, DFT, ASIC

vendor sign-off methodologies.

Knowledge of embedded processor architectures.

Experienced in writing technical specifications.

Verification experience is a big plus

BSEE is required.